Hello everyone,Long time no see. I was actually very busy with my job schedule and then also working on pipeline code. Well, I have successfully completed the pipelined version of the processor. I was working on32 bit but sadly, it had gotten corrupted and I was forced to work on 16 bit which I don’tContinueContinue reading “Verilog Code for 16 Bit MIPS Pipelined Processor”
Tag Archives: Verilog Codes
Verilog Code of 16 Bit RISC Processor with working
Verilog Code for the 16 bit RISC Processor Hello Everyone, I know many of you out there have been waiting for the working code for this processor along with RTL Schematic. Well, I have successfully coded the single cycle processor with R format Instruction, I format and Branch instructions too. I’ll start with my instruction first.ContinueContinue reading “Verilog Code of 16 Bit RISC Processor with working”
Gate Primitives
This page will describe GATE PRIMITIVES. These are used for synthesis in ASIC/FPGA tools and basically fits best for gate level simulation. The first few primitives are GATES FUNCTIONS NAND Performs nand operation between two operands NOR Performs nor operation between two operands OR Performs or operation between two operands AND Performs and operation betweenContinueContinue reading “Gate Primitives”
Verilog Code for MOD 6 Counter
As discussed in the previous post, I implemented the MOD 5 Counter. In this, I’ll implement MOD 6 Counter. This counter will have 6 states starting from 000 to 101 and then again back to zero. However, according to the equation below, ContinueContinue reading “Verilog Code for MOD 6 Counter”
Verilog Code for MOD 5 Counter
As discussed in the previous post, I implemented the MOD4 and MOD 8 Counters. In this, I’ll implement MOD 5 Counter. This counter will have 5 states starting from 000 to 100 and then again back to zero. However, according to the equation below, ContinueContinue reading “Verilog Code for MOD 5 Counter”
I2C Verilog Code and working
I had already made a post regarding I2C long ago, however, in this post I am reposting I2C but with various changes. Some changes involve the using of Acknowledgement Bit by the Slave and Master, Same SDA line for slave address, register address as well as data. No extra data line is required to readContinueContinue reading “I2C Verilog Code and working”
Verilog Code for VGA Interface
Verilog Code for VGA InterfaceVGA (Video Graphics Array) is a connection protocol used for display related activities and actions. It is basically the connection of cables to an output device. VGA are getting replaced by HDMI and micro HDMI cables but are still in use. A VGA connector pin has 15 connection pins. There areContinueContinue reading “Verilog Code for VGA Interface”
FPGA Simulation with Xilinx
How to simulate with FPGATo simulate your Verilog code you will need a FPGA. This tutorial willonly cover about simulating your program.Here are the things to gather up.FPGA Board USB CableXilinix ISim 14.2 or any versionBurner Software from your respective FPGA BrandWe are using here Diligent Basys2 FPGA and the software for its burning processContinueContinue reading “FPGA Simulation with Xilinx”
Deep Copy and Shallow Copy
System Verilog Shallow Copy and Deep CopyShallow CopyWhenever we create a variable for instantiating a class a name is created and then when new command is called then an object gets created. However assigning a new handle name with a prior handle will point to the same handle until new command has been executed.Example ParentContinueContinue reading “Deep Copy and Shallow Copy”
System Verilog Encapsulation
Data Hiding and EncapsulationAs for above codes and their outputs data inherited from the parent were visible to the world outside. One object can access others data. Even the super command gave all the permissions to access the codes. Yes that sounds like a science fiction movie where super keyword can access J.A.R.V.I.S database butContinueContinue reading “System Verilog Encapsulation”
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