Tutorials – Shashi’s Blog!!

FPGA Simulation with Xilinx

How to simulate with FPGATo simulate your Verilog code you will need a FPGA. This tutorial willonly cover about simulating your program.Here are the things to gather up.FPGA Board USB CableXilinix ISim 14.2 or any versionBurner Software from your respective FPGA BrandWe are using here Diligent Basys2 FPGA and the software for its burning processContinueContinue reading “FPGA Simulation with Xilinx”

Deep Copy and Shallow Copy

System Verilog Shallow Copy and Deep CopyShallow CopyWhenever we create a variable for instantiating a class a name is created and then when new command is called then an object gets created. However assigning a new handle name with a prior handle will point to the same handle until new command has been executed.Example ParentContinueContinue reading “Deep Copy and Shallow Copy”

System Verilog Encapsulation

Data Hiding and EncapsulationAs for above codes and their outputs data inherited from the parent were visible to the world outside. One object can access others data. Even the super command gave all the permissions to access the codes. Yes that sounds like a science fiction movie where super keyword can access J.A.R.V.I.S database butContinueContinue reading “System Verilog Encapsulation”

System Verilog Inheritance

System Verilog InheritanceSystem Verilog supports OOPS Inheritance which allows a user to inherit the class properties including the task, functions as well variables. System Verilog supports single inheritance as well as multiple inheritance. Elaboration – Consider a case where we have declared a class named parent and we want to its properties to be sharedContinueContinue reading “System Verilog Inheritance”

System Verilog Static Class and members

System Verilog Static Class MembersWhen we want to have some variable which we do not want to change its value across whole program and within all instances then static members come in action. Let us take an example like a counter which will count how many times a particular class was instantiated then it isContinueContinue reading “System Verilog Static Class and members”

System Verilog Class and Objects

System Verilog Classes and Objects A class is a blueprint or schematic which has its own behavior and works the same way for different instantiations. Any variable which is called or “instantiated” with the blueprint of this class is called an object of this class. Object Orientation revolves around classes and objects. It’s like solar systemContinueContinue reading “System Verilog Class and Objects”