OOPS – Shashi’s Blog!!

System Verilog Inheritance

System Verilog InheritanceSystem Verilog supports OOPS Inheritance which allows a user to inherit the class properties including the task, functions as well variables. System Verilog supports single inheritance as well as multiple inheritance. Elaboration – Consider a case where we have declared a class named parent and we want to its properties to be sharedContinueContinue reading “System Verilog Inheritance”

System Verilog Static Class and members

System Verilog Static Class MembersWhen we want to have some variable which we do not want to change its value across whole program and within all instances then static members come in action. Let us take an example like a counter which will count how many times a particular class was instantiated then it isContinueContinue reading “System Verilog Static Class and members”

System Verilog Class and Objects

System Verilog Classes and Objects A class is a blueprint or schematic which has its own behavior and works the same way for different instantiations. Any variable which is called or “instantiated” with the blueprint of this class is called an object of this class. Object Orientation revolves around classes and objects. It’s like solar systemContinueContinue reading “System Verilog Class and Objects”