Tag Archives: Master I2C

In my previous post, I explained working of I2C Verilog code. Same is continued here.https://gist.github.com/Shashi18/f8b60a492c1de87b3a34d26ae7b13ece.js else if(left_bits == 10)begin   if(sda == 0)begin   left_bits <= 1;   direction <= 1;   temp <= temp_reserved;  end  else begin   direction <= 1;   alpha <= 0;   left_bits <= left_bits + 1;  endendWhen the ACK/NACK is received at 9 then atContinueContinue reading “I2C Verilog Code Explanation II”

In this post, I am going to explain my previous post regarding I2C. You can visit the post by clicking here.https://gist.github.com/Shashi18/f8b60a492c1de87b3a34d26ae7b13ece.js INOUT  SDA: The SDA line is the inout port because Master will send data, address along this line as well as the Slave will send ACK/ NACK along the same SDA line hence it has toContinueContinue reading “I2C Verilog Code Explanation I”