Hello everyone,Long time no see. I was actually very busy with my job schedule and then also working on pipeline code. Well, I have successfully completed the pipelined version of the processor. I was working on32 bit but sadly, it had gotten corrupted and I was forced to work on 16 bit which I don’tContinueContinue reading “Verilog Code for 16 Bit MIPS Pipelined Processor”
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16-bit RISC Processor Verilog Code with Clock Gating
Clock Gating in 16-bit RISC ProcessorClock Gating is a technique where we provide a clock signal to a component or module only when it is needed. This is done to save power and only operate the running logic. This is mainly used in synchronous circuits.ContinueContinue reading “16-bit RISC Processor Verilog Code with Clock Gating”
Verilog Code of 16 Bit RISC Processor with working
Verilog Code for the 16 bit RISC Processor Hello Everyone, I know many of you out there have been waiting for the working code for this processor along with RTL Schematic. Well, I have successfully coded the single cycle processor with R format Instruction, I format and Branch instructions too. I’ll start with my instruction first.ContinueContinue reading “Verilog Code of 16 Bit RISC Processor with working”
Verilog Code for I2C with RTL Schematic
Hi Guys,Long time now. I was away dealing with my crappy life. Well, let’s move to the main point as the title of this post suggests. This I2C is very much less complicated than all my previous I2C Verilog codes. The biggest surprise to my readers in this post is that this I2C has an RTLContinueContinue reading “Verilog Code for I2C with RTL Schematic”
Gate Primitives
This page will describe GATE PRIMITIVES. These are used for synthesis in ASIC/FPGA tools and basically fits best for gate level simulation. The first few primitives are GATES FUNCTIONS NAND Performs nand operation between two operands NOR Performs nor operation between two operands OR Performs or operation between two operands AND Performs and operation betweenContinueContinue reading “Gate Primitives”
Verilog Code for MOD 6 Counter
As discussed in the previous post, I implemented the MOD 5 Counter. In this, I’ll implement MOD 6 Counter. This counter will have 6 states starting from 000 to 101 and then again back to zero. However, according to the equation below, ContinueContinue reading “Verilog Code for MOD 6 Counter”
Verilog Code for MOD 5 Counter
As discussed in the previous post, I implemented the MOD4 and MOD 8 Counters. In this, I’ll implement MOD 5 Counter. This counter will have 5 states starting from 000 to 100 and then again back to zero. However, according to the equation below, ContinueContinue reading “Verilog Code for MOD 5 Counter”
Verilog Code for MOD Counters
Counters are used to count and move the state of a circuit from one state to another. Whenever they are given a clock signal, either the system moves one state ahead or behind. It is not necessary to jump only one state. We can jump by a number of steps but for that, we wouldContinueContinue reading “Verilog Code for MOD Counters”
Setup Time and Hold Time
Setup time and Hold time are very important concepts when designing circuits. Compromising with these parameters would give an organized output. Whenever we see a circuit, we see it switching instantly ON and instantly OFF. It just appears like teleportation. Electronics from the low state were teleported to a higher state and vice versa. However,ContinueContinue reading “Setup Time and Hold Time”
Verilog simulation in Xilinx
Hi In this post, I am going to show you how to simulate a Verilog code in Xilinx ISE. I have included every step with an image so that the user can easily understand every step clearly. Ok let’s begin I am using Xilinx ISE version 14.2 You can have your own version of Xilinx or ModelSim or MultiSimContinueContinue reading “Verilog simulation in Xilinx”
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