This page will describe GATE PRIMITIVES. These are used for synthesis in ASIC/FPGA tools and basically fits best for gate level simulation.
The first few primitives are
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GATES
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FUNCTIONS
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NAND
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Performs nand operation between two operands
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NOR
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Performs nor operation between two operands
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OR
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Performs or operation between two operands
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AND
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Performs and operation between two operands
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XOR
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Performs exor operation between two operands
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XNOR
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Performs exnor operation between two operands
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NOT
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Performs not operation between two operands
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Here is the code that explains the above primitives.
The first letter within brackets is always an output and rest all are inputs.
Now I would show some transmission primitives.
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GATES
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FUNCTIONS
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Not
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Inverts the output
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Bufif0
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Passes the output if enable is low
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Bufif1
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Passes the output if enable is high
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Notif0
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Inverts value if enable is low
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Notif1
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Inverts value if enable is high
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Buf
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Passes the value
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Code –
Output –
Switch Primitives
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GATES
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FUNCTIONS
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Pmos
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Single direction p-mos
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Nmos
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Single direction n-mos
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Rpmos
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Resistive function p-mos
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Rnmos
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Resistive function n-mos
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Cmos
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Single direction cmos(both p and n mos)
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Rcmos
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Resistive cmos
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Pullup
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Pulls up the resistor
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Pulldown
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Pulls down the resistor
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Tranif0
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Bidirectional transistor if threshold is low
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Tranif1
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Bidirectional transistor if threshold is high
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All the switches pass from source to drain. Resistance will be introduced in R type primitives
Strength Values
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Strength Value
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SPECS
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7
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Supply Drive
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6
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Strong Pull
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5
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Pull Drive
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4
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Large Capacitance
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3
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Weak Drive
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2
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Medium Capacitance
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1
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Small Capacitance
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0
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High Impedance
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Let us have two input buffers A and B and a single output C. A has Pull Drive (pull0) and B has Large Capacitance (large) then according to table Pull drive is stronger than Large capacitance. So the output C will be A since A is stronger than B.
Gate and Switching delays.
Verilog consists of certain types of delays associated with gates.
Among those are
· Rise, fall, turn-off delays
· Minimal, Typical and Maximum Delays
The RISE DELAY is associated with the change of 0,x,z to 1.
The FALL DELAY is associated with the change of 1,x,z to 0.
The TURN-OFF DELAY is associated with the change of 0,1,x to Z.
The MINIMUM DELAY is associated with minimum delay a gate can have.
The MAXIMUM DELAY is associated with maximum delay a gate can have.
The TYPICAL DELAY is associated with average delay a gate can have.
Here is delay code.
Output Waveform –
Its clear output rises at 1ns as per rise delay and output d rises at typical rise delay of 2ns.
Minimum, Typical and Maximum delay are separated by : (colon). Rise, Turnoff and fall are separated by a comma.
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