Verilog Code for Down Counters

DOWN COUNTERS

Hola Amigos

Down Counter can be defined in a simple way don’t you think ?
It just counts. HaHa
Yes!! A counter just counts down from the maximum decimal value when all the required bits are 1 to zero.
Let me elaborate.
Let’s take an example of 3 bit counter. So whats the maximum of 3bit counter i.e when all bits are 1 in other words “111” It’s 7.
Similarly for 4 bits it “1111”that is 15.
Thus n-bits we require n Flip Flops.
Thus an Down counter will count from 15 down to 0 as I have stated and will again start from 15.
Lets code for a 4-bit Down Counter

module up(out,en,clk,reset);
output reg[7:0] out;
input en, clk, reset;
initial
out = 15;
always @(posedge clk)begin
if (reset) begin //if reset is true
out <= 8'b00001111 ;
end
else if (en==1 && out>0) //if enable is high // because 1111 is 15
out <= out - 1;
else
out <= 15;
end

endmodule
//*************************TestBench
module uptest();
reg en;
reg clk;
reg reset;
wire [7:0]out;

initial begin
reset=0;
clk=0;
en=1;
end

up call(out,en,clk,reset);
always #2 clk=!clk;
endmodule

 Here is the Output.
Notice the down counter and working again from 15  

Published by Shashi Suman

I am Shashi Suman. I am passionate about robots, 3D Printing, Verilog and automation. My current dream is make my own 3D printed intelligent robot.

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